Lead Design Verification Engineer

Location: Gliwice/ Warszawa - Poland

Position Description
If you have a very well-established knowledge of SoC design and you would like to prove yourself as a team leader or as an employee having an independent job position by realization of research and development tasks, this is an offer for you!

As a Lead Design Verification Engineer you will lead the verification process of various projects. You’ll organize, optimize and coordinate the following activities:

• Verifying the designing of electronic circuits
• Verifying the Systems-on-Chip (SoC)
• Creating new test environments
• Defining verification requirements for new projects and review verification requirements for already existing projects
• Supervising the work of other verification engineers in the product line (as a team leader)
• Take due care of the verification flow in the product line (as a team leader)

To complete the aforementioned projects you will use the following tools: Cadence NCSim, Cadence Verification Manager, Xilinx EDK.

Position Requirements

• Master of Science in Electrical / Computer Science
• Digital design experience
• Semiconductor IP design / FPGA design skills
• Established knowledge of object oriented programming / C++
• Experience in using SystemVerilog / SystemC / SVA
• Ability to use OVM / UVM TB will be an additional advantage
• Fluency in English
• Team management skills
• Good communication skills
• Organization and time management skills
• Knowledge of one of the following will be welcome: Linux system / serial communication protocols (e.g. USB, MIPI)/ interfacing NAND Flash memories / SDIO, SD, or e·MMC standards

Are you looking for challenges and further development? Do you want to work with people that share similar features and goals? Do you want to join a dynamic, growing team which creates solutions ahead of market expectations? If so, join us!

Apply to: [email protected]